Complementary Communication Path for Energy Efficient On-Chip Optical Interconnects

International audienceOptical interconnects are considered to be one of the key solutions for future generation on-chip interconnects. However, energy efficiency is mainly limited by the losses incurred by the optical signals, which considerably reduces the optical power received by the photodetectors. In this paper we propose a differential transmission of the modulated signals, which contributes to improve the transmission of the optical signal power on the receiver side. With this approach, it is possible to reduce the input laser power and increase the energy efficiency of the optical communication. The approach is generic and can be applied to SWSR-, MWSR-, SWMR- and MWMR-like architectures

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures

International audienceAs levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify their functional behavior (qualitative properties) and to predict their performance (quantitative properties). This paper presents the work currently done in the Multival project (pôle de compétitivité mondial Minalogic), in which verification and performance evaluation tools developed at INRIA and Saarland University are applied to three industrial architectures designed by Bull, CEA/Leti, and STMicroelectronics

3D advanced integration technology for heterogeneous systems

International audience3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description

Superconducting routing platform for large-scale integration of quantum technologies

To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspective in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al0.995Cu0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies and low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented

Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration

International audienceEven prior to the pandemic, there was increasing focus on enabling remote work and education. Although many companies have geographically distributed teams and students have moved to online instruction, remote working and learning has yet to become the norm despite the available technology and resources. There are many pros to remote meeting and education including increased flexibility, positive environmental benefits and improved work-life integration, but there are still tangible challenges when it comes to normalizing virtual interaction.Key challenges include effective communication, preventing isolation, and maintaining social connectivity. Being at the forefront of innovation, our community often leads technology adoption. Since the pandemic has been the catalyst for pushing new technologies forward, this provided an opportunity to explore how to shape the inevitable shift to more distributed and remote styles of working and learning.At the virtual 2021 International Solid-State Circuits Conference (ISSCC), we had the opportunity to have an event focused on remote learning, working, conferencing, and the future technologies that will improve all three. We had multiple distinguished speakers come talk about each of these topics using the Gather Town platform for presentations and the panel discussion. Ironically, during a discussion about going remote, the Gather Town platform experienced technical difficulties leading to no chance for a full panel discussion. We have re-invited the speakers to provide their perspectives on a few of the topics touched upon in their presentations

Formal Verification of CHP Specifications with CADP - Illustration on an Asynchronous Network-on-Chip

International audienceFew formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architectures described in the high-level language CHP, by using model checking techniques provided by the CADP toolbox. Our proposal is based on an automatic translation from CHP into LOTOS, the process algebra used in CADP. A translator has been implemented, which handles full CHP including the specific probe operator. The CADP toolbox capabilities allow the designer to verify properties such as deadlock-freedom or protocol correctness on substantial systems. Our approach has been successfully applied to formally verify two complex designs. In this paper, we illustrate our technique on an asynchronous Network-on-Chip architecture. Its formal verification highlights the need to carefully design systems exhibiting non-deterministic behavior

System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications

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In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization

International audienceAchieving the lowest possible operating voltage is needed to minimize the power consumption of a circuit but also to increase its reliability w.r.t hardware errors. An in-situ technique to estimate and reduce the design margins of a circuit is presented which significantly minimizes the operating voltage and tracks it during run-time operation of a circuit without failure. A DSP core embedding this technique has been fabricated and measured. Its V$_{min}$ has been estimated within +3.5%/-2.5% at nominal clock frequency (1600MHz), thus reducing by 19% its energy per operation

PROWAVES: Proactive Runtime Wavelength Selection for Energy-efficient Photonic NoCs

International audience2.5D manycore systems running parallel applications are severely bottlenecked by network-on-chip (NoC) latencies and bandwidth. Traditionally, network-on-chips are composed of electrical links that exhibit constrained bandwidth, increased energy consumption at high-speed communication, and long latencies. Photonic Network-on-Chips (PNoCs) have been shown to provide high bandwidth at low latencies and negligible data-dependent power. However, the power overheads of lasers, thermal tuning, and electrical-optical conversion present major challenges against wide-scale adoption of PNoCs. A primary factor that impacts PNoC power is the number of activated laser wavelengths in the system. Applications dynamic bandwidth needs provide the opportunity to selectively deactivate laser wavelengths when there is a lower bandwidth demand to alleviate high PNoC power concerns. This paper analyzes dynamic PNoC activity of applications at runtime so as to select laser wavelengths depending on an applications bandwidth requirements. The paper then proposes PROWAVES, a proactive runtime wavelength selection policy that forecasts the bandwidth needs and activates the minimum laser wavelengths for each application phase. We develop a cross-layer simulation framework to model the system performance, PNoC power and transient thermal distribution in a manycore system with PNoCs. We compare PROWAVES with prior system-level policies and our simulation results on a 2.5D system demonstrate that PROWAVES provides 18% and 33% power savings with only 1% and 5% loss in performance respectively, compared to activating all laser wavelengths in the system

High-Speed Design-for-Test Architecture for Asynchronous NoC-based Systems-on-Chip

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